A multi-element type chip resistor is already known as an example of a multi-element type chip device wherein a plurality of device elements are arranged on a single chip substrate in a row. Typically, a prior art multi-element type chip resistor has such a structure as shown in FIGS. 13 through 15.
As illustrated in FIGS. 13 through 15, the prior art multi-element type chip resistor has a chip substrate 10' made of an insulating material such as alumina ceramic. The substrate 10' has side edges which are spaced widthwise and formed with four pairs of longitudinally spaced projections 11'. The projections 11' in each pair are opposed to each other widthwise of the substrate. Each of the projections 11' has an upper surface formed with a thick-film primary electrode 12a' made of a conductive paste such as silver-palladium paste. A thick-film resistor element 13' made of ruthenium oxide paste for example is printed to bridge between each pair of primary electrode 12a'. The primary electrode 12a' is held in conduction with a secondary electrode 12b' extending onto the lower surface of the substrate 10'.
As shown in FIGS. 14 and 15, each resistor element 13' is normally covered by three thick-film printed glass layers which include an undercoat layer 14', a middle-coat layer 15' and an overcoat layer 16'. The undercoat layer 14' is provided to suitably perform laser trimming of the resistor element for resistance adjustment without surface roughening. The middle-coat layer 15' is provided to cover a laser-trimmed slit 17' (FIG. 13) of the resistor element 13'. The overcoat layer 16 protects the resistor element 13' as a whole.
Similarly to a single-element type chip resistor, the multi-element type chip resistor having the above-described structure may be conveniently manufactured by a master substrate 18' to which a thick-film printing method is performed, as shown in FIG. 16. The master substrate 18' is formed with vertical divisional grooves 19' and intersecting horizontal divisional grooves 20' for division into a plurality of unit substrates, as well as with through-holes 21' arranged along the horizontal divisional grooves 20'. The vertical divisional grooves 19' and the horizontal divisional grooves 20' may be formed, for example, by pressing blades against a surface of an non-baked substrate green sheet. The through-holes 21' may be formed by punching the same substrate green sheet.
In making multi-element type chip resistors, primary electrodes 12a' are simultaneously formed at respective regions of the master substrate 18' corresponding to the unit chips by printing and baking.
Then, resistor elements 13' are simultaneously formed by printing and baking.
Then, an undercoat layer 14' is simultaneously formed by printing and baking. At this stage, measuring probes (not shown) are brought into contact with each pair of electrodes 12a' while performing laser trimming (formation of a slit 17') until the corresponding resistor element 13' will have a target resistance.
Then, a middle-coat layer 15' and an overcoat layer 16' are successively formed by printing and baking.
Then, the master substrate 18' is divided along the horizontal divisional grooves 20', thereby providing substrate bars each including a plurality of longitudinally connected unit chip substrates.
Then, a conductive paste is applied to each substrate bar and baked to form secondary electrodes 12b' in conduction with the primary electrode 12a' on the obverse surface side.
Finally, the substrate bars are divided along the vertical divisional grooves 19', thereby providing a plurality of multi-element type chip resistors having the structure illustrated in FIGS. 13 through 15.
As appreciated from FIG. 13, each of the four resistor elements 13' formed on the same chip substrate 10' is symmetrical in plan view configuration with respect to an electrode-to-electrode center line C, and the width of the resistor element is enlarged longitudinally of the chip substrate 10' as much as possible. As shown in FIG. 14, on the other hand, the end edges 14a' of the undercoat layer 14' should be located beyond the resistor elements 13' at both ends of the chip substrate 10', whereas the middle-coat layer 15' and the overcoat layer 16' should have their respective end edges 15a', 16a' located beyond the end edges 14a' of the undercoat layer 14'. This is because, as represented in FIG. 13, the laser trimmed slit 17' starts from a side edge of the resistor element 13', thereby making necessary for the undercoat layer 14' to cover the resistor element 13' over its entire width. Further, since the undercoat layer 14' generally has a poor acid resistance, the middle-coat layer 15' and the overcoat layer 16' need to entirely cover the undercoat layer 14' to prevent corrosion thereof at the time of plating the electrodes with solder.
According to the prior art shown in FIG. 13, each resistor element 13' is wide and symmetrical (with respect to the electrode-to-electrode center line C), the dimension L.sub.1 between a side edge 10a' of the resistor element 13' at each end of the chip substrate 10' and the corresponding end edge 10a' of the chip substrate becomes small. As a result, it is extremely difficult to locate the respective end edges 14a', 15a', 16a' of the undercoat layer 14', middle-coat layer 15' and overcoat layer 16' within the small dimension L.sub.1 without any printing deviations.
If, due to a printing deviation or the like, part of the resistor elements 13' is exposed without being covered by any one of the glass layers, solder may deposit on the exposed part at the time of plating the electrodes with solder, thereby causing a shorting problem. Further, if the undercoat layer 14' is partially exposed by being incompletely covered by the middle-coat layer 15' and the overcoat layer 16', the undercoat layer 14' which is made of a material having a poor acid resistance may be corroded at the time of plating the electrodes with solder, and the solder may deposit on a resistor element to cause a shorting trouble.
A countermeasure for eliminating the problems caused by printing deviations of the respective glass layers is to drastically reduce the width of each resistor element 13'. However, such a countermeasure results in a new problem of reducing the range in which the resistance of the resistor element is adjusted by laser trimming.
Another countermeasure is to form the middle-coat layer 15' continuously over adjacent chip substrates (in the state before the master substrate 18' is divided). However, according to this countermeasure, the vertical divisional grooves 19' sectioning the adjacent chip substrates are filled with a hard glass material, so that division of the master substrate cannot be performed properly to result in irregularity in the configuration of the divided chip substrate. Further, glass fragments may scatter around at the time of dividing the master substrate, thereby deteriorating the surrounding environment.